Not applicable.
The present invention is related to synchronization of digital circuits without a phase locked loop (PLL). More specifically, the present invention relates to the method and apparatus of connecting multiple slave devices, for example regulators, such that the slave devices are synchronized in out of phase mode. Synchronizing switching converters in out of phase mode reduces noise and/or confines noise to known frequencies. Noise may be restricted to non-sensitive frequency bands or eliminated through the design and use of effective filters. Operating synchronized converters in this out of phase mode also reduces the ripple current requirement from the power supply feeding the converters.
The reduction, elimination or control of noise in electronic systems is a primary concern in design parameters. Noise, which is present in practically every electronic system, tends to limit signal precision and detectability in the electronic system. Electronic noise may be due to several sources and may be classified as one of several types, such as thermal (Johnson) noise, shot noise or flicker noise.
Thermal or Johnson noise is a function of temperature and is due to the random motion of electrons due to thermal agitation. Thermal noise is considered xe2x80x9cwhite noisexe2x80x9d since the rms value remains constant for all frequencies. Flicker noise however, is a function of frequency. Due to surface imperfections, electron conductance creates random current fluctuations, which increase at lower frequencies. In any case, the result is voltages or currents which accompany the desired signal and tend to contaminate it.
Solutions to electronic system noise have included the proper grounding of components in which undesired noise is subject to generation, as well as proper shielding of components. However this may only address some of the noise created. To increase the precision of certain electronic systems, greater measures need to be taken. To accomplish this, the characteristics and effects of electronic noise should be taken into account, and system operational solutions considered. Further, if noise can not be entirely eliminated, a method to contain the noise within known frequencies is a desirable alternative.
It is the object of the present invention to create a method and apparatus, which may be used to synchronize multiple slave devices, such as regulators or converters, in out of phase mode without a phase locked loop. Electronic system noise is thereby confined to non-sensitive frequency bands or is eliminated through the design and use of proper filters. The present invention achieves this goal by connecting each multiple slave device to a master device and to one another in series. A master clock signal is connected to each device clock input through a clock bus. The DH pin of the master device is connected to the first slave device PHIN pin and the DH pin of the first slave device is then connected to the PHIN pin of the second slave device. The DH pin of the second slave device is then connected to the PHIN pin of the third slave device and so on, for each slave device.
The internal clock for each slave device is held low until the PHIN pin for the slave device detects a DH or LX output from the previous device. Alternatively, a DL output from the previous device may be used in place of a DH or LX output. For the first slave device, the previous converter will be the master device and for the second slave device, the previous converter will be the first slave device. For the third slave device, the previous converter will be the second slave device and so on, for each slave device.
Once a DH, LX or DL connected signal is detected at the PHIN pin, the first subsequent rising edge of the master clock signal starts the internal clock of the slave device. Alternatively, the falling edge of the master clock signal may be used. For all the converters, the DH and LX output is synchronized with the rising edge of the internal clock of the slave device. Therefore, when the first slave device detects a DH, LX or DL signal from the master device, the first slave device internal clock starts and a DH signal is seen by the second slave device such that, the next subsequent rising edge of the master clock starts the internal clock of the second slave device. The DH and DL signal of each slave device is then used to drive a MOSFET transistor pair, such that each pair is driven out of phase.